The present embodiments relate to a memory circuit with leakage compensation of unselected memory cells.
Shrinking semiconductor integrated circuit feature sizes have placed increasing challenges on semiconductor integrated circuit design. In particular, minimum feature sizes of high density memory cells are frequently less than corresponding feature sizes of peripheral circuits. As a result, leakage current in unselected memory cells (ILEAK) may adversely affect correct sensing of a selected memory cell on a common bit line. This is particularly true of nonvolatile memories such as Flash EEPROM and ROM memories. However, this undesirable leakage current may also adversely affect standby current of volatile SRAM memories. Moreover, undesirable leakage current may compromise operation of both embedded memories in System on Chip (SoC) applications as well as stand-alone memories. Thus, there is a need to reduce leakage current in unselected memory cells for both nonvolatile and volatile memory systems. Accordingly, embodiments of the present invention described below are directed toward this and other improvements over the prior art.